In recent years, many semiconductor memory devices that include memory cells three-dimensionally in order to increase the degree of memory integration have been proposed (JP2007-266143A).
For example, one conventional semiconductor memory device that includes memory cells three-dimensionally uses transistors having a columnar structure (see JP2007-266143A). The transistors having a columnar structure include a columnar semiconductor layer having a columnar shape, a memory gate insulating layer, and multi-stacked conductive layers functioning as gate electrodes. The columnar semiconductor layer functions as a channel (body) of the transistors. The memory gate insulating layer is formed around the columnar semiconductor layer, and can store charges. The conductive layers are formed to surround the columnar semiconductor layer via the memory gate insulating layer. Such a three-dimensional structure can increase the memory capacity not by fine patterning but by multi-stacking, allowing process construction with techniques that are extended from conventional techniques.
In a manufacturing process of the above transistors having a columnar structure, electrical connection between the conductive layers and a wire provided above is formed via contact layers, which are formed to contact the multi-stacked conductive layers (gate electrodes) respectively. However, it is not easy to form the contact layers because they need to be formed to adjust to the height of the respective conductive layers. If the contact layers cannot be formed correctly, it is impossible to control the gates of the transistors accurately, spoiling the stability of the operation of the nonvolatile semiconductor memory device.